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1 ? fn6583.2 isl54065 negative signal swing, sub-ohm, dual spdt with click a nd pop elimination single supply switch with enable pin the intersil isl54065 device is a low on-resistance, low voltage, bi-directional, dual single-pole/double-throw (spdt) analog switch. it is designed to operate from a single +1.8v to +6.5v supply and pass signals that swing down to 6.5v below the positive supply rail. targeted applications include battery powered equipment that benefit from low r on (0.56 ), low power consumption (8na) and fast switching speeds (t on = 55ns, t off = 18ns). the digital inputs are 1.8v logic-compatible up to a +3v supply. the isl54065 also features integrated circuitry to eliminate click and pop noise to an audio speaker. the isl54065 is offered in a small form factor package, alleviating board space limitations. it is available in a tiny 12 ld 2.2x1.4mm tqfn. the isl54065 is a committed dual single-pole/double-throw (spdt) that consist of two normally open (no) and two normally closed (nc) switches with independent logic control. this configuration can be used as a dual 2-to-1 multiplexer. features ? pb-free (rohs compliant) ? single supply operation . . . . . . . . . . . . . . . . .+1.8v to +6.5v ? negative signal swing (max 6.5v below v+) ? enable pin to disable all switches ? integrated click and pop elimination circuitry ? click and pop circuitry disable pin ? on-resistance (r on ) - v+ = +4.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.52 - v+ = +4.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 - v+ = +2.7v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 - v+ = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 ?r on matching between channels . . . . . . . . . . . . . . . . . 10m ?r on flatness across signal range . . . . . . . . . . . . . . . . 0.33 ? low thd+n @ 32 load . . . . . . . . . . . . . . . . . . . . . . .0.02% ? low power consumption @ 3v (p d ). . . . . . . . . . . . 24nw ? fast switching action (v+ = +4.3v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ns ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kv ? guaranteed break-before-make ? 1.8v logic compatible (+3v supply) ? low i+ current when v inh is not at the v+ rail ? available in 12 ld 2.2mm x 1.4mm tqfn package applications ? audio and video switching ? battery powered, handheld, and portable equipment - mp3 and multimedia players - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? table 1. features at a glance isl54065 number of switches 2 sw spdt or 2-1 mux 4.3v r on 0.65 4.3v t on /t off 43ns/23ns 2.7v r on 0.9 2.7v t on /t off 55ns/18ns 1.8v r on 1.8 1.8v t on /t off 145ns/28ns packages 12 ld tqfn r on ( ) v com (v) 0 12 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -1 -2 -3 -4 -5 -6 i com = 100ma v+ = 1.8v v+ = 2.7v v+ = 4.5v on-resistance vs supply voltage vs switch voltage data sheet november 3, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6583.2 november 3, 2009 pinout (note 1) isl54065 (12 ld tqfn) top view note: 1. switches shown for en = logic ?1? and inx = logic ?0?. gnd v+ nc2 com2 no2 nc1 com1 no1 in1 in2 1 3 4 5 6 12 11 10 9 7 cp 2 en 8 click and pop circuitry pin descriptions pin function v+ supply voltage(+1.8v to +6.5v). decouple v+ to ground by placing a 0.1f capacito r at the v+ and gnd supply lines as near as the ic as possible. gnd ground connection inx input select pin en switch enable pin comx analog switch common pin nox analog switch normally open pin ncx analog switch normally closed pin cp click and pop circuitry enable pin truth table en in1 in2 nc1 nc2 no1 no2 0xxoffoffoffoff 1 0 0 on on off off 1 0 1 on off off on 110offononoff 1 1 1 off off on on note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL54065IRUZ-T* gg -40 to +85 12 ld thin tqfn (tape and reel) l12.2.2x1.4a *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic package d products employ special pb-free material sets; molding compounds/die attach materi als and nipdau plate - e4 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. isl54065
3 fn6583.2 november 3, 2009 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0v input voltages nox, ncx (note 2) . . . . . . . . . . . . . . . . (v+ - 7v) to ((v+) + 0.5v) inx, en (note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) output voltages comx (note 2) . . . . . . . . . . . . . . . . . . . (v+ - 7v) to ((v+) + 0.5v) continuous current nox, ncx, or comx . . . . . . . . . . . . . . 300ma peak current nox, ncx, or comx (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . 500ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kv thermal resistance (typical) ja (c/w) 12 ld tqfn package (note 3) . . . . . . . . . . . . . . . 155 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c power supply range . . . . . . . . . . . . . . . . . . . . . . . . +1.8v to +6.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. signals on ncx, nox, inx, en, cp, or comx exceeding v+ or gnd by the specified amount are clamped by internal diodes. limit f orward diode current to maximum current ratings. 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v, v en = v inh , v cp = v inl (note 4), unless otherwise specified. parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units analog switch characteristics on-resistance, r on v+ = 4.5v, i com = 100ma, v no or v nc = (v+ -6.5) to v+ (see figure 5) 25 - 0.52 - full - 0.68 - r on matching between channels, r on v+ = 4.5v, i com = 100ma, v no or v nc = voltage at max r on (note 8) 25 - 10 - m full - 13.1 - m r on flatness, r flat(on) v+ = 4.5v, i com = 100ma, v no or v nc = (v+ -6.5) to v+ (note 7) 25 - 0.11 - full - 0.14 - no or nc off leakage current, i no(off) or i nc(off) v+ = 5v, v com = -1.5v, 5v, v no or v nc = 5v, -1.5v 25 - -8.13 - na full - -0.4 - a com on leakage current, i com(on) v + = 5v, v com = -1.5v, 5v, v no or v nc = float 25 - -4.42 - na full - -0.33 - a dynamic characteristics turn-on time, t on v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 35 - ns full - 50 - ns turn-off time, t off v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 16 - ns full - 22 - ns break-before-make time delay, t d v+ = 5.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 3) full - 18 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 170 - pc off-isolation r l = 50 , c l = 5pf, f = 100khz, v no or v nc =1v rms (see figure 4) 25 - 60 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz, v no or v nc =1v rms (see figure 6) 25 - -75 - db total harmonic distortion f = 20hz to 20khz, v com = 0.5v p-p , r l = 32 25 - 0.02 - % -3db bandwidth v com = 1v rms , r l = 50 , c l = 5pf 25 - 60 - mhz nox or ncx off capacitance, c off f = 1mhz (see figure 7) 25 - 36 - pf comx on capacitance, c com(on) f = 1mhz (see figure 7) 25 - 88 - pf isl54065
4 fn6583.2 november 3, 2009 power supply characteristics positive supply current, i+ v+ = 5.5v, v inx = 0v or v+ 25 - 0.008 0.1 a full - 1.41 - a digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 2.4 - - v input current, i inh , i inl v+ = 5.5v, v inx = 0v or v+ 25 -0.1 - 0.1 a full - 0.3 - a electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v en = v+, v inh = 1.6v, v inl = 0.5v (note 4), unless otherwise specified . parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units analog switch characteristics on-resistance, r on v+ = 4.3v, i com = 100ma, v no or v nc = (v+ -6.5v) to v+ (see figure 5 ) 25 - 0.65 - full - 0.72 - r on matching between channels, r on v+ = 4.3v, i com = 100ma, v no or v nc = voltage at max r on (note 8) 25 - 10 - m full - 15 - m r on flatness, r flat(on) v+ = 4.3v, i com = 100ma, v no or v nc = (v+ -6.5v) to v+ (note 7) 25 - 0.1 - full - 0.14 - no or nc off leakage current, i no(off) or i nc(off) v+ = 4.3v, v com = -1.2v, 4.3v, v no or v nc = 4.3v, -1.2v 25 -0.1 - 0.1 a full -1 -0.33 1 a com on leakage current, i com(on) v + = 4.3v, v com = -1.2v, 4.3v, v no or v nc = float 25 -0.1 - 0.1 a full -1 -0.33 1 a dynamic characteristics turn-on time, t on v+ = 3.9v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 43 - ns full - 50 - ns turn-off time, t off v+ = 3.9v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 23.1 - ns full - 23.2 - ns break-before-make time delay, t d v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 3) full - 22 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 - 200 - pc off-isolation r l = 50 , c l = 5pf, f = 100khz, v no or v nc =1v rms (see figure 4) 25 - 60 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz, v no or v nc =1v rms (see figure 6) 25 - -75 - db total harmonic distortion f = 20hz to 20khz, v com = 0.5v p-p , r l = 32 25 - 0.025 - % nox or ncx off capacitance, c off f = 1mhz (see figure 7) 25 - 36 - pf comx on capacitance, c com(on) f = 1mhz (see figure 7) 25 - 88 - pf power supply characteristics positive supply current, i+ v+ = 4.5v, v in = 0v or v+ 25 -0.003 0.1 a full -0.9 - a electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v, v en = v inh , v cp = v inl (note 4), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units isl54065
5 fn6583.2 november 3, 2009 positive supply current, i+ v+ = 4.2v, v in = 2.85v 25 -0.78 12 a digital input characteristics input voltage low, v inl full -- 0.5 v input voltage high, v inh full 1.6 -- v input current, i inh , i inl v+ = 4.5v, v in = 0v or v+ 25 -0.5 - 0.5 a full - 0.2 - a electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v en = v+, v inh = 1.4v, v inl = 0.5v (note 4), unless otherwise specified parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units analog switch characteristics on-resistance, r on v+ = 2.7v, i com = 100ma, v no or v nc = (v+ -6.5v) to v+, (see figure 5) 25 - 0.9 - full - 0.96 - r on matching between channels, r on v+ = 2.7v, i com = 100ma, v no or v nc = voltage at max r on , (note 8) 25 - 10 - m full - 17 - m r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no or v nc = (v+ -6.5v) to v+, (notes 7, 9) 25 - 0.33 0.5 full - 0.35 0.55 dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 55 - ns full - 82 - ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf, (see figure 1) 25 - 18 - ns full - 24 - ns break-before-make time delay, t d v+ = 3.3v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 3) full - 30 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 - 150 - pc off-isolation r l = 50 , c l = 35pf, f = 100khz, v no or v nc =1v rms (see figure 4) 25 - 60 - db crosstalk (channel-to-channel) r l = 50 , c l = 35pf, f = 1mhz, v no or v nc =1v rms (see figure 6) 25 - -75 - db total harmonic distortion f = 20hz to 20khz, v com = 0.5v p-p , r l = 32 25 - 0.04 - % nox or ncx off capacitance, c off f = 1mhz (see figure 7) 25 - 36 - pf comx on capacitance, c com(on) f = 1mhz (see figure 7) 25 - 88 - pf digital input characteristics input voltage low, v inl 25 - - 0.5 v input voltage high, v inh 25 1.4 - - v input current, i inh , i inl v+ = 3.3v, v in = 0v or v+ 25 -0.5 - 0.5 a full - 0.2 - a electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v en = v+, v inh = 1.6v, v inl = 0.5v (note 4), unless otherwise specified . (continued) parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units isl54065
6 fn6583.2 november 3, 2009 electrical specifications - 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v en = v+, v inh = 1.0v, v inl = 0.4v (note 4), unless otherwise specified. parameter test conditions temp (c) min (notes 5, 6) typ max (notes 5, 6) units analog switch characteristics on-resistance, r on v+ = 1.8v, i com = 100ma, v no or v nc = (v+ -6.5v) to v+ (see figure 5) 25 - 1.87 - full - 1.97 - r on matching between channels, r on v+ = 1.8v, i com = 100ma, v no or v nc = voltage at max r on (note 8) 25 - 16 - m full - 30 - m r on flatness, r flat(on) v+ = 1.8v, i com = 100ma, v no or v nc = (v+ -6.5v) to v+, (note 7) 25 - 1.34 - full - 1.43 - dynamic characteristics turn-on time, t on v+ = 1.8v, v no or v nc = 1.8v, r l = 50 , c l = 35pf (see figure 1) 25 - 145 - ns full - 150 - ns turn-off time, t off v+ = 1.8v, v no or v nc = 1.8v, r l = 50 , c l = 35pf (see figure 1) 25 - 20 - ns full - 22 - ns break-before-make time delay, t d v+ = 1.8v, v no or v nc = 1.8v, r l = 50 , c l = 35pf (see figure 3) full - 130 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 - 40 - pc nox or ncx off capacitance, c off f = 1mhz (see figure 7) 25 - 36 - pf comx on capacitance, c com(on) f = 1mhz (see figure 7) 25 - 88 - pf digital input characteristics input voltage low, v inl 25 - - 0.4 v input voltage high, v inh 25 1.0 - - v input current, i inh , i inl v+ = 2.0v, v in = 0v or v+ 25 -0.5 - 0.5 a full - 0.19 - a notes: 4. v in = input voltage to perform proper function. 5. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. flatness is defined as the difference bet ween maximum and minimum value of on-resist ance over the specified analog signal ran ge. 8. r on matching between channels is calculated by s ubtracting the channel with the highest max r on value from the channel with lowest max r on value, between nc1 and nc2 or between no1 and no2. 9. limits established by characterization and are not production tested. isl54065
7 fn6583.2 november 3, 2009 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection figure 3a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 3b. test circuit figure 3. break-before-make time 50% t r < 5ns t f < 5ns t off 90% v+ 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on + ----------------------- - = switch input logic input v out r l c l com no or nc in 50 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v+ 0v c l v out r g v g gnd com no or nc v+ c logic input in repeat test for all switches. 90% v+ 0v t bbm logic input switch output 0v v out logic input in com r l c l v out 35pf 50 no nc v+ gnd v nx c isl54065
8 fn6583.2 november 3, 2009 figure 4. off-isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit figure 8a. click and pop waveform figure 8b. click and pop test circuit figure 8. click and pop elimination test circuits and waveforms (continued) analyzer r l signal generator v+ c 0v or v+ no or nc com in gnd signal direction through switch is reversed, worst case values are recorded. *50 source v+ c 0v or v+ no or nc com in gnd v nx v 1 r on = v 1 /100ma 100ma 0v or v+ analyzer v+ c no1 or nc1 signal generator r l gnd in x com1 50 nc com2 nc2 or no2 signal direction through switch is reversed, worst case values are recorded. *50 source v+ c gnd no or nc com in impedance analyzer 0v or v+ com is connected to no or nc during on capacitance measurement. t d vdc v inx * * v inx waveform for click and pop elimination on nox terminal. for click and pop elimination on ncx terminal invert inx. t d = 200ms measured at 50% points. 0v 0v t d click and pop circuitry r l 220f 220f inx comx ncx nox vdc vdc isl54065
9 fn6583.2 november 3, 2009 detailed description the isl54065 is a bidirectional, dual single pole-double throw (spdt) analog switch that offers precise switching from a single 1.8v to 6.5v supply with low on-resistance (0.83 ) and high speed operation (t on =55ns, t off = 18ns). the device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8v), low power consumption (8na), and a tiny 2.2x1.4mm tqfn package. the low on-resistance and ron flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. the isl54065 contains esd protection diodes on each pin of the ic (see figure 9). these diodes connect to either a +ring or -ring for esd protection. to prevent forward biasing the esd diodes to the +ring, v+ must be applied before any input signals, and the input signal voltages must remain between recommended operating range. if these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the foll owing two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the v+ rail. logic inputs can be protected by adding a 1k resistor in series with the logic input (see figure 9). the resistor limits the input current below the threshold that produces permanent damage. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting external schottky diodes to the signal pi ns will shunt the fault current to the v+ supply instead of through the internal esd diodes thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current. power-supply and by-pass considerations the isl54065 construction is ty pical of most single supply cmos analog switches, in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog vo ltage limits. unlike switches with a 5.5v maximum supply voltage, the isl54065?s 6.5v maximum supply voltage provides plenty of head room for the 10% tolerance of 5v supplies due to overshoot and noise spikes. the minimum recommended supply voltage is 1.8v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to ?electrical specifications ? tables, beginning on page 3, and ?typical performance curves?, beginning on page 11, for details. v+ and gnd also power the internal logic and level shifters. the level shifters convert the input logic levels to v+ and gnd signals levels to drive the analog switch gate terminals. a high frequency decoupling capacitor placed as close to the v+ and gnd pin as possible is recommended for proper operation of the switch. a value of 0.1f is highly recommended. negative signal swing capability the isl54065 contains circuitry that allows the analog switch signal to swing below ground. the device has an analog signal range of 6.5v below v+ up to the v+ rail (see figure 16) while maintaining low r on performance. for example, if v+ = 5v, then the analog input signal range is from -1.5v to +5v. if v+ = 2.7v then the range is from -3.8v to +2.7v. click and pop operation the isl54065 contains circuitry that prevents audible click and pop noises that may occur when audio sources are powered on or off. single supply audio sources are biased at a dc offset that can generate tr ansients during power on/off. a dc blocking capacitor is needed to remove the dc bias at the speaker load. for 32 headphones, a 220f capacitor is typically used to preserve the audio bandwidth. the power gnd v comx v ncx v+ logic inputs v nox -ring +ring clamp 1k figure 9. overvoltage protection isl54065
10 fn6583.2 november 3, 2009 on/off transients are ac coupled by the 220f capacitor to the speaker load causing a click and pop noise. the isl54065 has shunt switches on the no and nc pins to eliminate click and pop transients (see figure 10). these switches are driven complimentar y to the main switch. when nc is connected to com, the sh unt switch is active on the no pin (and vice versa). the shunt switches connect an impedance (140 typical, see figure 25) from the no/nc pin to ground to discharge any transients that may appear on the no or nc pins. when the dc bias becomes active at the source, the no and nc terminals will also have a dc offset due to capacitor dv/dt principle. the dc offset will be discharged through the shunt impedance on the no and nc terminals instead of the speaker, eliminating click an d pop noise. on the isl54065, the click and pop circuitry is enabled when the cp pin is logic high (>1.4v). the click and pop circuitry may be disabled by tying the cp pin low (<0.4v). *under high impedance loads (20k ) such as the input impedance of pre-amplifiers, the com terminal voltage may rise due to small leakage currents charging the com capacitance. this is not seen when low impedance (32 ) loads such as headphones are used because the small leakage currents does not result in significant potential drop across the load. if the user desires to reduce the voltage build up on the com pin, a 1k to ground may be placed on the com pin. this impedance is small enough to reduce the voltage build up significantly while not increasing the power dissipation dramatically. curren t consumption considerations will need to be taken for driving a smaller load impedance under this scenario. click and pop with enable pin click and pop elimination can be driven with the enable pin by setting it low. having the enable pin low turns off the main switches (no and nc) while the click and pop circuitry will be active. transient voltages due to power on/off from both sources will be shunted to ground. for proper click and pop elimination the enable pin should be driven high at least 200ms after any source transients occurs to avoid audible transients at the speaker load. click and pop with input select pin click and pop elimination can also be driven with the input select pin. when inx = 0, the nox terminals are connected to the shunt impedance. when inx = 1, the ncx terminals are connected to the shunt impeda nce. in this situation, only one of the source transient voltages will be shunted to ground, depending on the input select state. the input select pin should be driven 200ms after any source transients occurs to prevent audible transients at the speaker load. logic-level thresholds this switch family is 1.8v cmos compatible (0.45v v olmax and 1.35v v ohmin ) over a supply range of 1.8v to 3.3v (see figure 16). at 3.3v the v il level is 0.5v maximum. this is still below the 1.8v cmos guaranteed low output maximum level of 0.45v, but noise margin is reduced. at 3.3v the v ih level is 1.4v minimum. while this is above the 1.8v cmos guaranteed high output minimum of 1.35v under most operating conditions the switch will recognize this as a valid logic high. the digital input stages draws a larger supply current whenever the digital input voltag e is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. the isl54065 has been designed to mi nimize the supply current whenever the digital input voltage is not driven to the supply rails (0v to v+). for example driving the device with 2.85v logic high while operating with a 4.2v supply the device draws only 1a of current. high-frequency performance in 50 systems, the isl54065 has an on switch -3db bandwidth of 60mhz (see figure 21). the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor across the open terminals and ac couples higher frequencies, resulting in signal feed-through from a switch?s input to its output. off-isolation is the resistance to this feed-through. crosstalk indicates the amount of feed-through from one switch channel to another switch channel. figure 22 details the high off-isolation and crosstalk rejection provided by this part. at 100khz, off-isolation is about 60db in 50 systems, decreasing approximately 2 0db per decade as frequency in com r l 220f 32 no nc v+ gnd c audio source a 220f r sh audio source b r sh p cp en isl54065 figure 10. click and pop operation isl54065
11 fn6583.2 november 3, 2009 increases. at 1mhz, crosstalk is about -75db in 50 systems, decreasing approximately 20db per decade as frequency increases. leakage considerations reverse esd protection diode s are internally connected between each analog-signal pin, v+ and gnd. one of these diodes conducts if any analog signal exceeds the recommended analog signal range. virtually all the analog switch leakage current comes from the esd diodes and reversed bi ased junctions in the switch cell. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased to either the +ring or -ring and the analog input signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the +ring or -ring and the reverse biased junctions at the internal switch cell constitutes the analog-signal-path leakage current. typical performance curves t a = +25c, unless otherwise specified figure 11. on-resistance vs supply voltage vs switch voltage figure 12. on-resistance vs switch voltage figure 13. on-resistance vs switch voltage figure 14. on-resistance vs switch voltage r on ( ) v com (v) 0 12 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -1 -2 -3 -4 -5 -6 i com = 100ma v+ = 1.8v v+ = 2.7v v+ = 4.5v 0 0.30 r on ( ) v com (v) 0.35 0.40 0.45 0.50 0.60 0.65 0.70 0.75 0.80 0.85 0.95 0.90 1.00 0.55 -3-2-1 12345 i com = 100ma v+ = 4.5v t = +85c t = +25c t = -40c r on ( ) v com (v) 0 0.30 0.35 0.40 0.45 0.50 0.60 0.65 0.70 0.75 0.80 0.85 0.95 0.90 0.55 -3-2-1 12345 1.00 i com = 100ma v+ = 4.3v t = +85c t = +25c t = -40c r on ( ) v com (v) 0 1.05 0.35 0.45 0.65 0.75 0.85 0.95 0.55 -3 -2 -1 1 2 3 4 -5 -4 1.15 1.25 i com = 100ma v+ = 2.7v t = +85c t = +25c t = -40c isl54065
12 fn6583.2 november 3, 2009 figure 15. on-resistance vs switch voltage figure 16. analog signal range vs supply voltage figure 17. charge injection vs switch voltage figure 18. digital switching point vs supply voltage figure 19. turn - on time vs supply voltage figure 20. turn - off time vs supply voltage typical performance curves t a = +25c, unless otherwise specified (continued) r on ( ) v com (v) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 -3 -2 -1 1 2 3 6-5-4 i com = 100ma v+ = 1.8v t = +85c t = -40c t = +25c -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 1.52.02.53.03.54.04.55.05.5 6.0 analog signal range (v) supply voltage (v) signal max signal min q (pc) v com (v) 0 50 100 150 012345 -1 -2 -3 -4 -5 6 v+ = 4.5v v+ = 3.3v v+ = 2.0v absolute values v+ = 5.5v 200 250 300 350 400 450 500 550 600 650 700 absolute values v+ (v) v inh and v inl (v) 1.52.02.53.03.54.04.5 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 v inh v inl 0.2 0.1 0 1.6 1.5 1.4 1.3 1.2 t on (ns) v+ (v) t = +85c t = -40c t = +25c 1.8 3.3 4.5 5.5 0 20 40 60 80 100 120 140 160 t off (ns) v+ (v) 1.8 3.3 4.5 5.5 0 20 40 5 10 15 25 30 35 t = +85c t = -40c t = +25c isl54065
13 fn6583.2 november 3, 2009 figure 21. frequency response figure 22. crosstalk and off isolation figure 23. click and pop elimination 20k load 200ms delay figure 24. click and pop elimination 32 load 200ms delay typical performance curves t a = +25c, unless otherwise specified (continued) frequency (hz) 0 -1 normalized gain (db) v in = 1v rms @ 0vdc offset r l = 50 v+ = 1.8v to 5.5v -2 -3 -4 -5 1k 100k 1m 100m 10k 10m 1g frequency (hz) -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) off-isolation crosstalk 1k 10k 100k 1m 10m 100m v in = 1v rms @ 0vdc offset r l = 50 v+ = 1.8v to 5.5v v dc (1v/div) inx (1v/div) v no (500mv/div) time ( 200ms/div) v dc = 1.5vdc r l = 20k v+ = 3v *see page 10: click and pop operation *v com (10mv/div) v dc (1v/div) inx (1v/div) v no (500mv/div) v com (10mv/div) v dc = 1.5vdc r l = 32 v+ = 3v time (200ms/div) isl54065
14 fn6583.2 november 3, 2009 figure 25. shunt resistance vs switch voltage figure 26. total harmonic distortion vs frequency die characteristics substrate potential (powered up): gnd (dfn paddle connection: tie to gnd or float) transistor count: 432 process: submicron cmos typical performance curves t a = +25c, unless otherwise specified (continued) 50 75 100 125 150 175 200 225 250 275 300 325 350 -5 -4 -3-2-10 123456 switch voltage (v) shunt resistance ( ) v+ = 4.3v v+ = 3v v+ = 1.8v v+ = 5v frequency (hz) 20 100 200 1k 2k 10k 20k v bias = 0vdc r l =32 v+ = 3.3v 707mv rms 177mv rms 0.01 0.02 0.03 0.04 0.05 thd+n (%) 0 360mv rms isl54065
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6583.2 november 3, 2009 isl54065 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x index area 2 1 n nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x c 0.05 c a 0.10 c a1 leads coplanarity 0.10 m c a b 0.05 m c pin #1 id 5 (datum b) (datum a) nx l nd ne 3 e nx b 12 bottom view side view top view 10 2.30 0.40 0.45 (12x) 1.50 1 2 3 0.25 (12x) 0.40 typical recommended land pattern l12.2.2x1.4a 12 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.15 2.20 2.25 - e 1.35 1.40 1.45 - e 0.40 bsc - k0.20- - - l 0.35 0.40 0.45 - n122 nd 3 3 ne 3 3 0-124 rev. 0 12/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, re- spectively. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be ei- ther a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. same as jedec mo-255uabd except: no lead-pull-back, "a" min dimension = 0.45 not 0.50mm "l" max dimension = 0.45 not 0.42mm. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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